The present invention relates to a pulse width modulation system, and in particular, to a pulse width modulation system for controlling a power converter.
FIG. 18 shows an example of a power converter using a pulse width modulation system. In FIG. 18, the reference numeral 1 refers to AC power supply, 2 to a rectifier circuit, 3 to a smoothing capacitor, 4 to a motor, 5 to a current detector, 6 to a PWM control unit, 7 to a current detection unit, 8 to a motor control unit, Qu, Qv, Qw, Qx, Qy and Qz to switching elements, and 10 to the power converter. Voltage supplied from the AC power supply 1 is rectified by the rectifier circuit 2, and further, smoothed by the smoothing capacitor 3, to be converted to DC voltage. By switching the switching elements Qu, Qv, Qw, Qx, Qy and Qz, the DC voltage is converted to a U-phase voltage, a V-phase voltage and a W-phase voltage connected to the motor 4.
Further, the current detector 5 detects a DC current Idc that flows from the switching elements Qx, Qy and Qz to the smoothing capacitor 3. And, the current detection unit 7 detects a U-phase motor current Iu, a V-phase motor current Iv and a W-phase motor current Iw based on the DC current Idc detected by the current detector 5 and from gate signals Gu, Gv, Gw, Gx, Gy and Gz outputted by the PWM control unit 6.
Based on the detected motor currents Iu, Iv and Iw and a speed command Fr* given from the outside, the motor control unit 8 outputs a U-phase AC voltage command Eu, a V-phase AC voltage command Ev, and a W-phase AC voltage command Ew. And, based on the AC voltage commands Eu, Ev and Ew, the PWM control unit 6 outputs the gate signals Gu, Gv, Gw, Gx, Gy and Gz that instruct respective switching elements Qu, Qv, Qw, Qx, Qy and Qz. Here, the power converter 10 comprises the rectifier circuit 2, the smoothing capacitor 3, the current detector 5, the PWM control unit 6, the current detection unit 7, the motor control unit 8, and the switching elements Qu, Qv, Qw, Qx, Qy and Qz.
FIG. 19 shows a configuration of the PWM control unit 6. The PWM control unit 6 comprises a carrier generation unit 601, a U-phase comparing unit 602, a V-phase comparing unit 603, a W-phase comparing unit 604, and reversing units 605, 606 and 607. The carrier generation unit 601 outputs a carrier C as a triangular wave of a frequency Fc, based on a carrier frequency command Fc. The U-phase comparing unit 602, which outputs the gate signal Gu, compares the U-phase AC voltage command Eu with the carrier C, and outputs an H level when the U-phase AC voltage command Eu is larger, and outputs an L level when smaller. Further, the reversing unit 605, which outputs the gate signal Gx, outputs the H level when the gate signal Gu is L level, and outputs the L level when the gate signal Gu is H level. Similarly, the V-phase comparing unit 603, which outputs the gate signal Gv, compares the V-phase AC voltage command Ev with the carrier C, and outputs the H level when the V-phase AC voltage command Ev is larger, and outputs L level when smaller. Further, the reversing unit 606, which outputs the gate signal Gy, outputs the H level when the gate signal Gv is L level, and outputs the L level when the gate signal Gv is H level. Further, the W-phase comparing unit 604, which outputs the gate signal Gw, compares the W-phase AC voltage command Ew with the carrier C, and outputs the H level when the W-phase AC voltage command Ew is larger and L level when smaller. Further, the reversing unit 607, which outputs the gate signal Gz, outputs the H level when the gate signal Gw is L level and outputs the L level when the gate signal Gw is H level.
Next, operation of the PWM control unit 6 will be described. FIG. 20 is a waveform chart for various parts including the PWM control unit, and its horizontal axis is a time axis. Each waveform will be described in turn from the top. In FIG. 20, (a) shows waveforms of the AC voltage commands Eu, Ev and Ew and a waveform of the carrier C for pulse width modulation of the AC voltage commands Eu, Ev and Ew.
In FIG. 20, (b) shows a waveform of the gate signal Gu obtained by comparing the U-phase AC voltage command Eu with the carrier C. The waveform becomes H level when the U-phase AC voltage command Eu is larger than the carrier C, and becomes L level when the U-phase AC voltage command Eu is smaller than the carrier C. When the gate signal Gu is H level, the gate signal Gx becomes L level, and at that time, the switching element Qu becomes on and the switching element Qx becomes off. On the other hand, when the gate signal Gu is L level, the gate signal Gx becomes H level, and at that time, the switching element Qu becomes off and the switching element Qx becomes on.
In FIG. 20, (c) shows a waveform of the gate signal Gv that is obtained by comparing the V-phase AC voltage command Ev with the carrier C. That waveform becomes H level when the V-phase AC voltage command Ev is larger than the carrier C, and becomes L level when the V-phase AC voltage command Ev is smaller than the carrier C. A relation between the gate signals Gv and Gy, and operations of the switching elements Qv and Qy are similar to the relation between the gate signals Gu and Gx and the operation of the switching elements Qu and Qx, respectively.
In FIG. 20, (d) shows a waveform of the gate signal Gw that is obtained by comparing the W-phase AC voltage command Ew and the carrier C. The waveform becomes H level when the W-phase AC voltage command Ew is larger than the carrier C, and becomes L level when the W-phase AC voltage command Ew is smaller than the carrier C. A relation between the gate signals Gw and Gz, and operation of the switching elements Qw and Qz are similar to the relation between the gate signals Gu and Gx and the operation of the switching elements Qu and Qx, respectively.
In FIG. 20, (e) shows a waveform of a line voltage Vuv between a U-phase output to which the switching element Qu is connected and a V-phase output to which the switching element Qv is connected, out of line voltages as outputs of the power converter.
In FIG. 20, (f) shows waveforms of currents that flow from the power converter 10 to the motor 4. Here, the symbol Iu refers to the U-phase motor current, Iv to the V-phase motor current, and Iw to the W-phase motor current. The U-phase motor current Iv, the V-phase motor current Iv and the W-phase motor current Iw correspond to the U-phase output to which the switching element Qu is connected, the V-phase output to which the switching element Qv is connected, and the W-phase output to which the switching element Qw is connected, respectively.
In FIG. 20, (g) shows a waveform of the DC current Idc. By turning on and off the switching elements, based on the gate signals, the outputs of the power converter, i.e., the U-phase voltage, the V-phase voltage and the W-phase voltage with respect to the lower terminal (cathode) of the smoothing capacitor 3 have waveforms similar to the gate signals Gu, Gv and Gw, respectively. As a result, the line voltage Vuv of the motor becomes the voltage shown in the figure. As described above, the PWM control unit 6 outputs the gate signals Gu, Gv and Gw, by comparing the carrier C with the AC voltage commands Eu, Ev and Ew, respectively.
Next, referring to FIG. 21, a method of detecting the motor currents Iu, Iv and Iw in the current detection unit 7 will be described.
FIG. 21 shows details of the period T1 in FIG. 20. In FIG. 21, the horizontal axis indicates time, and the vertical axis indicates the gate signal Gu, the gate signal Gv, the gate signal Gw, the line voltage Vuv, a line voltage Vvw between the V-phase output and the W-phase output, a line voltage Vwu between the W-phase output and the V-phase output, and the DC current Idc, in turn from the top. As shown in FIG. 20, the sign of the V-phase motor current Iv is plus, and the signs of the U-phase motor current Iu and the W-phase motor current Iw are minus.
In the period Ta, all the gate signals Gu, Gv and Gw are L level, and thus, the switching elements Qu, Qv and Qw are off, and the switching elements Qx, Qy and the Qz are on. Accordingly, the current flowing to the motor 4 flows from the switching element Qy through the V-phase output to the motor 4, and flows from the motor 4 through the U-phase output and W-phase output to the switching elements Qx and Qz, respectively, to return to the switching element Qy. Thus, current does not flow to the current detector 5, and Idc is zero.
In the period Tb, the gate signal Gv is H level and the gate signals Gu and Gw are L level, and thus, the switching elements Qx, Qv and Qz are on, and the switching elements Qu, Qy and Qw are off. Accordingly, the current flowing to the motor 4 flows from the upper terminal (anode) of the smoothing capacitor 3 through the switching elements Qv and the V-phase output to the motor 4, and flows from the motor 4 through the U-phase output and W-phase output to the switching elements Qx and Qz respectively, to the cathode of the smoothing capacitor 3. Accordingly, current having the same strength and sign as the current Iv flows to the current detector 5.
In the period Tc, the gate signals Gv and Gw are H level and the gate signal Gu is L level, and thus, the switching elements Qx, Qv and Qw are on and the switching elements Qu, Qy and Qz are off. Accordingly, the current flows from the anode of the smoothing capacitor 3 through the switching element Qv and the V-phase output to the motor 4, and at the same time, through the switching element Qw and the W-phase output to the motor 4. Further, the current that has flowed to the motor 4 flows from the motor 4 through the U-phase output and the switching element Qx, to the cathode of the smoothing capacitor 3. Accordingly, current having the same strength as and the opposite sign to the current Iu flows to the current detector 5.
In the period Td, all the gate signals Gu, Gv and Gw are H level, and thus, the switching elements Qu, Qv and Qw are on and the switching elements Qx, Qy and Qz are off. Accordingly, the current flowing to the motor 4 flows from the switching element Qv through the V-phase output to the motor 4, and flows from the motor 4 through the U-phase output and W-phase output to the switching elements Qu and Qw respectively, to return to the switching element Qv. Thus, current does not flow to the current detector 5, and Idc is zero.
In the period Te, the state of the gate signals is same as the period Tc, and accordingly, current having the same strength as and the opposite sign to the current Iu flows to the current detector 5. In the period Tf, the state of the gate signals is same as the period Tb, and accordingly, current having the same strength and sign as the current Iv flows to the current detector 5. In the period Tg, the state of the gate signals is same as the period Ta, and accordingly, current does not flow to the current detector 5.
The current detection unit 7 detects current synchronously with the gate signals. For example, operation of the current detection unit 7 in the period T1 is as follows. Namely, in the period Tb or Tf, the DC current Idc as the output of the current detector 5 is sampled to detect the V-phase motor current Iv. In the period Tc or Te, by sampling the DC current Idc as the output of the current detector 5 and by reversing the sign, the U-phase motor current Iu is detected. Further, since the sum total of the currents flowing from the power converter to the motor is zero, the W-phase motor current Iw is obtained by the following equation (1):
Iw=xe2x88x92(Iu+Iv)xe2x80x83xe2x80x83Eq. (1) 
Although kinds of currents that can be detected differ depending on a combination of the gate signals, two motor currents can be detected out of the three motor currents. And, the remaining current can be easily obtained from the fact that the sum total of the currents is zero.
As techniques relating to this kind of apparatus, Japanese Unexamined Patent Laid-Open Nos. 6-153526 and 4-236171 are known, for example.
Among the waveforms shown in FIG. 20, ones in the period T2 are enlargedly shown in FIG. 22. The horizontal and vertical axes of the waveforms shown in FIG. 22 are same as the FIG. 21. Here, we note the periods Tj and Tl. In the periods Tj and Tl, the gate signals Gv and Gw are H level, and the gate signal Gu is L level. Thus, the switching elements Qx, Qv and Qw are on, and the switching elements Qu, Qy and Qz are off.
Current flows from the anode of the smoothing capacitor 3 through the switching element Qv and the V-phase output to the motor 4, and at the same time, through the switching element Qw and the W-phase output to the motor 4. The current that has flowed to the motor 4 flows from the motor 4 through the U-phase output and the switching element Qx, to the cathode of the smoothing capacitor 3. Accordingly, current having the same strength as and the opposite sign to the current Iu flows to the current detector 5. Thus, when the DC current Idc is detected by the current detector 7 in the periord Tj or Tl, the current Iu can be detected.
Although FIG. 22 shows ideal waveforms that rise instantaneously, current has a rise delay time actually. In some cases, overshoot occurs in the DC current Idc. Accordingly, when a period is short such as the periods Tj and Tl, it is difficult to sample correct current values.
As seen from FIG. 22, a sampling period becomes short when a pulse width of a line voltage becomes narrow. Namely, when a line voltage is low, and when the frequency of the carrier is high, sampling becomes difficult. When the frequency of the carrier is smallered in order to ensure a sufficient sampling period, then, motor control performance reduces and magnetic sound from the motor increases.
Hereinabove, the most general three-phase case has been taken as an example. However, the same applies to the single-phase case or multi-phase case of more than three phases, too. In the case of the single phase, there are four gate signals as the outputs of the PWM control unit, and two are in reversed relation to the other two.
FIG. 23 shows waveforms of two gate signals and the DC current. Two gate signals obtained by reversing are omitted. Similarly to the three-phase case, when a difference between the gate signals is narrow in width, pulse width of the DC current becomes narrow and its detection becomes difficult.
Further, in the case of multi-phase of more than three phases, for example, five phases, the number of the gate signals is ten, and five is in reversed relation to the other five. FIG. 24 shows waveforms of five gate signals except for the other five obtained by reversing, and of the DC current. In this case too, similarly to the three-phase case, when width of a difference between gate signals is narrow, pulse width of the DC current becomes narrow, and its detection becomes difficult.
According to the principle of the pulse width modulation, when a difference between AC voltage commands as modulated waves becomes smaller, i.e., a line voltage is smaller, width of a difference between gate signals becomes narrower as in the above.
To solve the above problems, the present invention provides a method of pulse width modulation of a plurality of signals, wherein: said plurality of signals are corrected such that widths of pulses obtained based on a signal difference of each two signals out of said plurality of signals become larger than or equal to a predetermined value given in advance.
The said signal difference is obtained by adding an integrated error to a difference between said two signals; and at the same time, when said signal difference is less than said predetermined value, at least one of said two signals is corrected such that the difference between said two signals becomes zero or less than said signal difference; and when said signal difference is larger than or equal to the predetermined value, at least one of said two signals is corrected such that the difference between said two signals becomes said signal difference.
By this, when the signal difference is less than the predetermined value, the signal difference is corrected to be larger than or equal to the predetermined value. Thus, by modulating the corrected signals, it is ensured that the pulse width as a result of modulation is larger than or equal to a predetermined value. Further, when, in obtaining the integrated error, the signal difference is less than the predetermined value, the signal difference becomes zero and the integrated error increases. The signal difference increases as the integrated error increases, and thus, the signal difference becomes larger than or equal to the predetermined value in the course of time, and at that time the pulse width modulation is performed.
Further, the present invention provides a method of performing pulse width modulation on a plurality of signals, using a carrier, wherein: signal differences, each of which is a difference between two signals out of said plurality of signals, are obtained; and when at least one of said signal differences lies in a neighborhood of zero, a frequency of said carrier is lowered.
By this, in an area where the pulse width of a difference between pulses as the results of the modulation becomes smaller if the present invention is not applied, the carrier frequency becomes lower. When the carrier frequency becomes lower, the pulse width becomes wider, and the required pulse width can be ensured.
Further, the present invention provides a power converter to which each of the above-described methods of performing the pulse width modulation is applied, with voltage commands being inputted as signals, and with output pulses serving as output voltages. By this, it is possible to ensure the required pulse width of the line voltage as a difference between output voltages.